LD39100S33R

The LD39100S33R features ultra-low output noise of 6uVrms typical (10Hz to 100kHz bandwidth). This is achieved through internal noise reduction circuitry and careful bandgap design. The low noise is maintained across the operating current range (1mA to 1A) and temperature range (-40°C to +125°C). For comparison, standard LDOs typically have 50-100uVrms noise. This exceptional noise performance makes it ideal for powering sensitive analog circuits, precision ADCs, and RF sections where power supply noise directly impacts system performance.

For noise-sensitive applications, this LDO provides clean power without additional filtering.

The LD39100S33R has a typical dropout voltage of 200mV at 1A output current and 25°C. Dropout voltage increases slightly at higher temperatures (approximately 250mV at 125°C). At lighter loads, dropout is proportionally lower (100mV at 500mA, 40mV at 100mA). To maintain regulation, the input voltage must be at least Vout + Vdropout. For 3.3V output at 1A, minimum input is 3.5V. This low dropout allows efficient operation from 3.6V Li-Ion batteries even as they discharge to 3.5V.

Ensure minimum input voltage accounts for dropout at maximum load and temperature.

The LD39100S33R provides excellent Power Supply Rejection Ratio (PSRR) of 90dB at 1kHz, 75dB at 10kHz, and 50dB at 100kHz. This means ripple on the input is attenuated by 90dB (31,600x) at 1kHz. The high PSRR effectively filters switching noise from upstream DC-DC converters, eliminating the need for additional LC filters in many applications. At higher frequencies, PSRR decreases but remains effective for most switching converter frequencies (100kHz-1MHz). The PSRR is measured with 1Vpp input ripple and 100mA load current.

High PSRR eliminates need for additional filtering in most applications. Verify PSRR at your switching frequency.

The LD39100S33R is stable with ceramic output capacitors as small as 1uF, though 10uF is recommended for best transient response. Use X5R or X7R ceramic capacitors with low ESR (<100mΩ). Place the capacitor within 5mm of the output pin with short traces. For applications with large load transients (>100mA steps), increase to 22uF or add a small series resistor (0.1-0.5Ω) to improve stability. Tantalum or aluminum electrolytic capacitors can also be used but provide less benefit due to higher ESR.

Use 10uF ceramic minimum. Increase for large load transients or long output traces.

The LD39100S33R includes comprehensive protection features: Current limit protection activates at approximately 1.5A, limiting output current during overload conditions; Thermal shutdown disables the output when junction temperature exceeds 150°C, with 15°C hysteresis for recovery; Safe operating area protection prevents damage during high-input low-output voltage conditions; Internal discharge circuit rapidly discharges output capacitor when disabled (in shutdown-capable variants). These protections ensure robust operation and prevent damage during fault conditions.

Built-in protections make this LDO suitable for unattended and safety-critical applications.

Power dissipation is calculated as Pd = (Vin - Vout) × Iout + (Vin × Ignd). For example, at Vin = 5V, Vout = 3.3V, Iout = 1A: Pd = (5 - 3.3) × 1 = 1.7W. The SOT-223 package has thermal resistance Rth(j-a) of approximately 60°C/W on standard PCB. At 1.7W, junction temperature rise is 102°C above ambient. For Ta = 25°C, Tj = 127°C, which is within the 150°C maximum. For higher power or elevated ambient, improve thermal design with copper area, thermal vias, or heatsinks.

Calculate worst-case power dissipation and verify junction temperature. Improve thermal design if needed.