SiC MOSFET Module Application Guide
Introduction to SiC Technology
Silicon Carbide (SiC) MOSFETs offer superior performance compared to silicon IGBTs including higher switching speeds, lower losses, and higher temperature operation. This guide covers the key design considerations for using Starpower SiC MOSFET modules.
Gate Drive Requirements
SiC MOSFETs require specific gate drive conditions for optimal performance. Recommended gate voltage is +18V for turn-on and -3V to -5V for turn-off. The negative turn-off voltage is critical for immunity against high dv/dt transients. Gate resistance should be 5-10Ω for fast switching while controlling EMI.
PCB Layout Guidelines
Proper PCB layout is essential for SiC MOSFET performance. Minimize gate loop inductance by using short, wide traces and placing the gate driver close to the module. Use Kelvin source connection to eliminate source inductance effects. Place decoupling capacitors close to the module terminals.
Thermal Management
SiC MOSFETs can operate at higher junction temperatures (up to 175°C) than silicon devices, but proper thermal management is still critical. Calculate losses based on RDS(on) at operating temperature and switching frequency. Design cooling system to maintain acceptable junction temperature under worst-case conditions.
Protection Considerations
SiC MOSFETs have limited short-circuit withstand time (2-5μs) compared to IGBTs. Implement fast overcurrent protection with response time <2μs. Use desaturation detection or shunt-based current sensing. Implement soft turn-off to prevent overvoltage spikes during fault conditions.
EMI Management
The high switching speed of SiC MOSFETs (dv/dt >50V/ns) can generate significant EMI. Implement proper filtering, shielding, and layout techniques to meet EMI requirements. Common mode filters and snubber circuits may be necessary depending on application requirements.
💡 FAE Insights
📋 Customer Cases
Power Electronics
Solution
Redesigned gate drive with proper damping resistors and minimized loop inductance
Results
Eliminated oscillations, achieved clean switching, passed EMI testing
Frequently Asked Questions
1. Why is negative gate voltage required for SiC MOSFETs?
Negative gate voltage (-3V to -5V) is critical for SiC MOSFETs due to: (1) High dv/dt immunity - SiC switches with dv/dt >50V/ns, which can capacitively couple through Cgd and cause false turn-on. Negative VGS ensures gate stays below threshold during high dv/dt. (2) Miller effect - during turn-off, high dv/dt causes current through Cgd that can raise gate voltage. Negative bias provides margin. (3) Threshold voltage variation - Vth can be as low as 2V; negative bias ensures reliable off-state. (4) Noise immunity - industrial environments have high noise levels; negative bias improves immunity. Without negative bias, false turn-on can cause shoot-through and module failure. Starpower strongly recommends -3V minimum, -5V preferred for high dv/dt applications.
2. What is the recommended PCB layout for SiC MOSFET modules?
Recommended PCB layout for Starpower SiC modules: (1) Gate loop - minimize inductance with short (<20mm), wide (>2mm) traces. Use dedicated gate return (Kelvin source). Target <10nH gate loop inductance. (2) Power loop - minimize DC bus loop area with laminated busbars or parallel planes. Target <50nH power loop inductance. (3) Decoupling - place 100nF-1μF ceramic capacitors within 10mm of module terminals. Use multiple vias to ground plane. (4) Gate driver - place within 25mm of module with direct connection to gate and Kelvin source pins. (5) Shielding - use ground planes and shielding for EMI control. (6) Thermal - use thermal vias under module mounting area. Starpower provides detailed layout examples in application notes.
3. How do I protect SiC MOSFETs from overcurrent faults?
SiC MOSFET overcurrent protection requires fast response (<2μs): (1) Detection methods: (a) Desaturation detection - monitor VDS during on-state; >7V indicates fault. Response time <1μs. (b) Shunt resistor - use low-inductance shunt with fast comparator. Response time <500ns. (2) Soft turn-off - gradual gate discharge (10-20μs) to prevent overvoltage spikes. (3) Gate clamping - active Miller clamp maintains negative voltage during fault. (4) Current limiting - implement cycle-by-cycle current limiting in control loop. (5) Fuse protection - semiconductor fuse for catastrophic failure. Key differences from IGBT: SiC has 2-5μs tSC vs 10μs for IGBT, requiring faster protection. SiC's fast switching actually helps by quickly limiting fault current once detected.
4. What EMI considerations are important for SiC designs?
EMI considerations for SiC MOSFET designs: (1) High dv/dt - SiC generates dv/dt >50V/ns, creating high-frequency EMI up to 100MHz+. (2) Common mode currents - high dv/dt drives currents through parasitic capacitances to ground. (3) Mitigation strategies: (a) Slow down switching with higher gate resistance (trade-off: higher losses). (b) Use common mode chokes on input/output lines. (c) Implement proper shielding and grounding. (d) Use snubber circuits to reduce voltage overshoot. (e) Filter design - LC filters with cutoff <1MHz for conducted EMI. (4) Layout - minimize loop areas, use ground planes, separate power and signal grounds. (5) Testing - plan for 30-50% more filtering than equivalent IGBT design. Starpower provides EMI test data and mitigation guidelines.